Novice Gospel: An Overview of Some Common Mistakes in Learning FPGAs

1, not familiar with the internal structure of the FPGA, do not understand the basic principles of programmable logic devices.

Why is FPGA programmable? I am afraid many rookies don't know, and they don't want to know. Because they think this is irrelevant. They subconsciously think that it is programmable, it is definitely like writing software. The idea of ​​software programming is ingrained, and seeing Verilog or VHDL is like seeing C or other software programming languages. The reading of a strip, the analysis of a strip. If these rookies have always refused to understand why the FPGA is programmable, and do not understand the internal structure of the FPGA, it is a myth to learn FPGA. Although the EDA software is now very advanced, it can be integrated with the cat-like painting software, but perhaps only God knows what the EDA software is finally combining. Maybe a light, it’s okay to run a horse. This is why many rookies have learned N for a long time and still be a rookie.

So why can an FPGA be "programmed"?

First, let's take a look at what is called "Cheng". In fact, "Cheng" is nothing more than a bunch of 01 codes with certain meaning. Programming is actually writing these 01 codes. However, we now have a lot of development tools, usually not directly write these 01 code, but in the form of high-level language, and finally converted to this 01 code by the development tool. For software programming, the processor has a special decoding circuit to translate these 01 codes into various control signals one by one, and then control its internal circuits to perform one operation or other operations. So the software is read one by one, because the operation of the software is done step by step. The FPGA is programmable, and the essence is to rely on these 01 codes to achieve its function changes, but the difference is that FPGA can perform different functions, instead of relying on software to translate 01 code and then control an arithmetic circuit, FPGA There are no such things.

There are three main blocks in the FPGA: programmable logic cells, programmable connections, and programmable IO modules.

There are three main blocks in the FPGA: programmable logic cells, programmable connections, and programmable IO modules.

What is a programmable logic unit? Its basic structure consists of a 4-input or 6-input 1-output "truth table" made of a certain memory (SRAM, FLASH, etc.) plus a D flip-flop. Any 4-input 1-output combination logic circuit has a corresponding "truth table". Similarly, if you use such a memory to make a 4-input and 1-output "truth table", you only need to modify its "truth table". The internal value can be equivalent to any combination of 4 inputs and 1 output. What are the internal values ​​of these “truth tables”? That is the 01 code only. What if you want to implement a sequential logic circuit? This is not a D flip-flop. Any timing logic can be converted to a combinatorial logic + D flip-flop. But after all, only the logic circuit of 4 input and 1 output is realized. Usually, the scale of the logic circuit is quite large. then what should we do? This time you need to use the programmable connection. There are a lot of memory-controlled link points on these wires. By overwriting the values ​​of the corresponding memories, you can determine which lines are connected and which are broken. This allows many programmable logic cells to be combined to form large logic circuits. Finally, programmable IO, this is actually a must pay attention to FPGA as a chip-level use. Any chip must have an input pin and an output pin. Programmable IO can arbitrarily define a non-dedicated pin (specific non-user-usable test and download pins in the FPGA) as input or output, and can also set the IO level standard.

In a word, FPGAs are programmable because they can be created into a single "truth table" with special 01 code, and these "truth tables" can be combined to achieve large-scale logic functions. Without understanding the internal structure of the FPGA, you can't understand how the final code changes into the FPGA. It is impossible to understand in depth how to fully utilize the FPGA. Today's FPGAs are not only the three blocks mentioned above, but also a lot of dedicated hardware functional units. How to use these units to implement complex logic circuit design is an obstacle that must be overcome from the rookie to the master. All of this must start with understanding the internal logic of the FPGA and its working principle.

2, misunderstanding the HDL language, how to see the hardware structure.

The full English name of the HDL language is: Hardware DescripTIon Language, pay attention to the word DescripTIon instead of Design. Why should the foreigner use the word DescripTIon instead of Design? Because HDL is not used to design hardware, it is only used to describe the hardware.


The description of the word accurately reflects the nature of the HDL language. The HDL language is just a textual representation of a known hardware circuit, but only the later circuits are described in the form of text. Before writing the language, the hardware circuit should have been designed. Language is just a matter of translating this design into a textual expression. However, many people don't understand it. Since the hardware has been designed, it is finished directly to the production department. Why should it be converted into a textual expression and then through the troublesome process of EDA tools? In fact, this is the problem that many rookies do not understand the abstract level of design. Any design, including clothing, machinery, and advertising design, has an abstract level of problems. Let's take the ad design. The original design may be a concept. Designing this concept is just an idea. It is far from the final advertisement. Hardware design also has different levels of abstraction, and each level needs to be designed. The highest level of abstraction is algorithm level, followed by architecture level, register transfer level, gate level, and physical layout level.

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